Download ExaScale Computing Study: Technology Challenges in Achieving by Peter Kogge (Editor & Study Lead) PDF

By Peter Kogge (Editor & Study Lead)

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Additional bandwidth is gained because this arrangement allows accesses to be pipelined both in terms of outgoing commands and returning data. A typical contemporary microprocessor has latencies of 1 cycle, 20 cycles, and 200 cycles to the L1 cache, L2 cache, and external DRAM respectively. Memory systems such as FB-DIMM actually increase such latencies substantially because of the pipelined nature of the card-to-card protocol. These latencies make the penalty for a cache miss very high and motivate the use of latency-hiding mechanisms.

6 Companion Studies Concurrent with this study were two other activities with significant synergism. First is a DoEsponsored study entitled “Simulation and Modeling at the Exascale for Energy, Ecological Sustainability and Global Security (E3SGS)”4 , whose goal is to set the stage for supercomputer-class Exascale applications that can attack global challenges through modeling and simulation. A series of town-hall meetings was held in order to develop a more complete understanding of the properties of such applications and the algorithms that underly them.

1 Mitigation Mitigation strategies are often employed to help overcome the various losses in the electricity delivery system. For example: • UPS: At these power levels, many data centers choose to forgo UPS protection for the compute nodes and only use the UPS to enable graceful shutdown of the disk subsystem (a small fraction of the overall computer power dissipation). In the case where the UPS is used for the entire data center, DC power is an increasingly studied option for reducing losses.

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